1. Field of the Invention
The present invention relates to a voltage level shifter and a level shifting method for shifting a small range signal to a wide range signal.
2. Description of the Related Art
Generally, laptop computers and portable devices require low power consumption, and widely adopt a multi-power architecture which implements a small range voltage and a wide range voltage are used. Typically, such multi-power architectures require level-shifting circuits to provide voltage and power driving interfaces between circuits operating at different power voltage levels. Such level shifting circuits commonly include an input buffer receiving an input signal driven at a first power supply voltage level, a level shifting circuit for shifting the operating level of the input signal to a second power supply voltage level, an output buffer circuit which operates at the second voltage level, and a pull-up/pull-down circuit.
In such conventional circuits, the pull-up/pull-down circuit is implemented as integrated circuits including, for example, diode-connected transistors or resistors. These conventional circuits commonly occupy a large area and induce additional static current consumption.
FIG. 1 is a circuit diagram of a conventional low-to-high voltage level shifter.
Referring to FIG. 1, the conventional level shifter has an input buffer 110, a level shifting circuit 120, an output buffer 130 and a pull-up/pull-down circuit 140.
The conventional level shifter shifts an input signal having a small range to a wide range signal.
The input buffer 110 includes a first inverter 112 having a PMOS transistor M1′ and an NMOS transistor M2′, and a second inverter 114 having a PMOS transistor M3′ and an NMOS transistor M4′. The input buffer 110 is activated by a first power voltage VADDL having a low voltage level. The input signal LI is buffered by the first inverter 112 and the second inverter 114. A first small range signal having the same logic level as the input signal LI is outputted via a node N2′. A second small range signal having a reverse logic with respect to the input signal LI is outputted via a node N1′.
The level shifting circuit 120 includes a cross-coupled pair having PMOS transistors M5′, M7′, and NMOS transistors M6′, M8′. The level shifting circuit 120 is activated by a second power voltage VADDH having a high voltage level. Furthermore, the level shifting circuit 120 shifts the small range input signal to a wide range signal by using a positive feedback circuit. In particular, the level shifting circuit 120 shifts first and second small range signals to a first wide range signal via a node N3′ and a second wide range signal via node N4′.
The output buffer 130 has PMOS transistors M9′ and M11′, and NMOS transistors M10′, M12′. The output buffer 130 is activated by the second power voltage VADDH. The first wide range signal at the node N3′ and the second wide range signal at the node N4′ are determined by a logic state of the input signal LI. The output buffer 130 buffers the first and second wide range signals, and transforms the first and second wide range signals into third and fourth wide range signals that have enough power to drive an output load. The third and fourth wide range output signals are output via nodes N7 and N8, respectively. The third wide range signal has the same logic state as the input signal LI, and the fourth wide range signal has the reverse logic state with respect to the input signal LI.
The pull-up/pull-down circuit 140 has a pull-up transistor M13′ and a pull-down transistor M14′. The pull-up/pull-down circuit 140 is activated by the second power voltage VADDH. When a low voltage stage does not operate, the pull-up/pull-down circuit 140 maintains an output node voltage as a predetermined logic state based on pull down or pull up control signals PD and PDB so as to avoid an undefined logic state of the wide range signals. The pull down or pull up control signals PD and PDB are generated by an external source. The pull-up control signal PDB has a reverse logic status with respect to the pull-down control signal PD, or may have logic status irrelevant to the pull-down control signal PD.
Hereinafter, the operation of the conventional level shifter is illustrated with reference to FIG. 1.
When the small range input signal LI having a low-voltage logic level ‘HIGH’ is inputted to first inverter 112, the node N2′ has the low-voltage logic level ‘HIGH’ and the node N1′ has the low-voltage logic ‘LOW’. The transistor M6′ of the level shifting circuit 120 is turned on by the logic ‘HIGH’ of the node N2′, and the transistor M8′ is turned off by the logic ‘LOW’ of the node N1′. Thus, a current path including the transistor M5′ and M6′ are disabled.
A logic level of the node N3′ is ‘LOW’ and the transistor M7′ is turned on by the logic ‘LOW’ of the node N3′. Because the transistor M7′ is turned on, the logic level of the node N4′ is a high-voltage logic level ‘HIGH’, so that the transistor M5′ is turned off. Thus, a current path including the transistor M7′ and M8′ is disabled.
The high-voltage logic level ‘HIGH’ is substantially the same as VADDH and the high-voltage logic level ‘LOW’ is substantially the same as VSS. Furthermore, when the small range input signal LI has the low-voltage logic level ‘LOW’, the logic level of the node N3′ is high-voltage logic level ‘HIGH’ and the logic of the node N4′ is high-voltage logic level ‘LOW’.
When the small range input signal LI having a low-voltage logic level ‘LOW’ is inputted to first inverter 112, the node N2′ has the low-voltage logic level ‘LOW’ and the node N1′ has the low-voltage logic ‘HIGH’.
The output buffer 130 buffers the output signal of the nodes N3′ and N4′ having the logic levels defined by the logic state of the input signal LO, and outputs a third wide range signal (a voltage of the node N7′) having the same logic status as the input signal L1 and a fourth wide range signal (a voltage of the node N8′) having the reverse logic state with respect to the input signal LI. The third and fourth wide range signals have enough power to drive an output load.
When the first power voltage VADDL has a substantially ground level, in the conventional level shifter, the transistors M6′ and M8′ turned off due to the logic state ‘LOW’ of the input signal L1, the node N1′ voltage, and the node N2′ voltage. In addition, the node N3′ and N4′ are in floating state.
Furthermore, when the floated node N3′ and N4′ reach a high level enough to turn off transistors M5′ and M7′, transistors M5′, M6′, M7′ and M8′ are turned off and nodes N3′, N4′ have an unknown logic state or a floating state.
When the node N4′ (or node N3′) has a voltage level low enough to turn on the transistor M5′ (or transistor M7′), a positive feedback loop formed by the transistors M5′ and M7′ is activated. By the positive feedback loop, one of the nodes N3′ and N4′ has the high-voltage logic level ‘HIGH’, and the other node of the nodes N3′ and N4′ has a floating state.
In particular, in the case in which the node N4′ has a voltage level low enough to turn on the transistor M5′, the transistor M5′ is turned on and the node N4′ is in the floating state due to the high-voltage logic level ‘HIGH’ of the node N3′. Furthermore, in the case in which the node N3′ has a voltage level low enough to turn on the transistor M7′, the node N3′ is in the floating state due to the high-voltage logic level ‘HIGH’ of the node N4′.
In the case in which the node N3′ (or node N4′) has an unknown logic status, the logic level of the node N3′ (or node N4′) varies depending upon a fabrication condition of the level shifter, a peripheral circuit condition or noise. Accordingly, when the pull-up circuit or the pull-down circuit is not used, the third wide range signal (the voltage at the node N7′) or the fourth wide range signal (the voltage at the node N8′) is in the unknown logic status, and the level shifter may no longer output correct wide range signals.
When the first power voltage VADDL is disabled, a power of first power voltage ADDL is not supplied, or a voltage level of the first power voltage VADDL decreases to a ground level, the first power voltage VADDL has substantially a ground level GND. The pull-up circuit or the pull-down circuit prevents the unknown logic state of the third and fourth wide range signals.
When the pull-up/pull-down circuit 140 integrated by an integrated circuit of transistors may have an area smaller than a pull-up/pull-down circuit integrated by an integrated circuit of diode-connected transistors or resistors. However, the pull-up/pull-down circuit 140 realized by the integrated circuit may consume large static current and requires separate control signals (PDB, PD of FIG. 1) for controlling the transistors M13′ and M14′.
That is, when the low voltage stage is disabled by the disabled first power voltage VADDL, the conventional level shifter additionally requires a pull-up/pull-down circuit that consumes a static current so as to maintain the third and fourth wide range signals as definite logic state. Furthermore, the conventional level shifter needs the separate control signals for selecting a normal operation or a pull-up/pull-down operation.
When the pull-up/pull-down circuit integrated by an integrated circuit of diode-connected transistors or resistors occupies a large area and induces additional static current consumption.